Built-in self-tests (BIST) are typically performed to determine defective array structures in a chip. BISTs are utilized to test various types of memory. Typically, in a random access memory (RAM), a BIST can test for many types of faults. These faults can be broadly placed into four categories: (1) Stuck at faults; (2) Transition faults; (3) Coupling faults; and (4) Neighborhood Pattern Sensitive faults.
RAMs have both read and write ports. Therefore, these faults may be sensitized by writing specific data patterns to the RAM memory and reading out the same specific data patterns. The data that is read out can then be compared to the data that was read in to the memory to determine whether any faults exist. Faults in write/read address decoders, write/read word lines, and read data path circuits are also covered while testing for the above-mentioned faults in a BIST of RAM.
However, there is an important difference between a BIST for RAM and a BIST for a read-only memory (ROM) memory array. The ROM is a read-only structure and, therefore, generally only has read ports. Consequently, the ability for a BIST to provide a writing pattern to the ROM that can then be read out to test for special fault sensitizing patterns is not possible in a ROM memory.
ROM memory cells are hardwired to either power or ground depending on the content in the cell. As a result, stuck at faults are the most commonly occurring faults in the ROM memory cells. These stuck at faults may include: Stuck at Cell faults, Stuck at Word-Line faults, Stuck at Bit-Line faults, Stuck at Address Input Line faults, Stuck at Decoder faults, and Mixed Stuck at faults (a combination of above mentioned faults).
Other types of faults that may occur in a ROM, though less common, are Delay faults (back-to-back read may be one reason) and Power Voltage Sensitive faults. Furthermore, dynamic faults may occur in a ROM from read word lines or read data path circuits. As on-die ROMs normally operate at a full speed clock (e.g., microprocessor internal pipeline clock), these dynamic faults cannot be ignored.
Existing ROM BIST algorithms compress pre-silicon ROM content and store the compressed signature either in the same ROM or off-ROM. Then, during a power-on BIST of the chip, the contents are read out, compressed, and the results are compared with the pre-silicon signature. For conventional ROM BIST algorithms, this signature is calculated using a single way Cyclic Redundancy Check (CRC) algorithm. As a result, an escape probability for static faults compared to multi-way CRC signature algorithms is higher. Yet, conventional ROM BIST algorithms do not provide a robust way to test static faults in the ROM using the conventional hardware for ROM BIST.
Furthermore, reading out the contents of ROM post-silicon usually involves a simple shift register as a Read Side Test Register (RSTR) and a Linear Feedback Shift Register (LFSR) for compressing the serial data shifted out of the RSTR. As a result, every read cycle must be interleaved with multiple shift cycles so that compression can take place properly. Consequently, back-to-back reads cannot take place and, therefore, back-to-back read word line faults sensitization and read data path delay faults sensitization are not possible. The alternative to this is to use a Multiple Input Shift Register (MISR) as the RSTR. But, this is costly in terms of hardware. Existing algorithms for ROM BIST do not cover testing for dynamic faults using the conventional combination of a simple shift register as RSTR and LFSR for compressing.